The present invention relates to dynamic random access memory, and, more specifically, to connecting heritage dynamic random access memory in a high-speed dynamic random access memory environment.
Dynamic random access memory (DRAM) is a general-purpose high-performance memory device suitable for use in a broad range of applications. DRAM allows high bandwidth for multiple, simultaneous, randomly addressed memory transactions. Many kinds of DRAM have been utilized, such as fast page mode (FPM) DRAM, extended data output (EDO) DRAM, synchronous DRAM (SDRAM), and Rambus(copyright) DRAM (RDRAM). Newer kinds of DRAM, such as RDRAM, typically have better performance than earlier kinds of DRAM, such as EDO DRAM. Earlier kinds of DRAM with respect to the age of a given computer system may be referred to as heritage DRAM with respect to that computer system. Hence the use of the newer kinds of DRAM is generally preferred over the use of heritage DRAM in computer systems.
A chipset for implementing the functions of a motherboard in a computer system may interface with a preferred type of DRAM, typically a high-speed DRAM, but may also contain compatibility circuitry for allowing the use of heritage DRAM. For example, a chipset for a personal computer motherboard may have optimal performance with SDRAM but may also include circuitry to interface with heritage DRAM types such as FPM DRAM. Reasons for including compatibility circuitry for heritage DRAM may include the fact that a customer may already have large stocks of heritage DRAM in inventory or that temporary shortages of the preferred memory type may exist in the marketplace.
Among the highest-speed memory performances currently available utilize RDRAM. The RDRAM is a synchronous DRAM operating in data packet mode at very high clock rates (e.g. at 400 MHz), and transfers data on both falling and rising edges of the RDRAM clock (e.g. at 800 MHz). With respect to processors utilizing RDRAM, normal SDRAM is a heritage DRAM type. For various reasons, including those given above, it may be advantageous to provide an interface for SDRAM in a primarily RDRAM motherboard environment.
Earlier motherboards could readily accommodate SDRAM, EDO DRAM, and FPM DRAM because of similarities in clocking and data presentation. However, RDRAM differs from SDRAM in clock rate and phase, data packet configuration, and signaling logic levels. Utilizing large amounts of buffering memory would be inefficient and costly.
A method and apparatus for synchronizing a synchronizing clock is disclosed. This method and apparatus includes generating an initial synchronizing clock from a reference clock. It then includes receiving a synchronizing packet utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to received data of the synchronizing packet.